As CMOS (complementary metal-oxide semiconductor) technologies are scaled, SRAM stability becomes a major concern. It is apparent that scaling of six transistor (6-T) SRAM cells will not be able to keep up with overall technology scaling. Stability problems arise whenever the stored voltages on the internal nodes are disturbed. In 6-T cells, this occurs when the pass-gate connected to an internal node with a stored ‘0’ is activated with a ‘1’ on the bit line. This pulls the internal node above ground, which could unintentionally flip the cell. Two scenarios result in such a situation in a given cell: during a read event and during a write to a neighboring cell with a common word line (column/bit select).
FIG. 1 is a schematic diagram illustrating a six transistor (6-T) memory cell 100 known in the art. This cell 100 is particularly well-suited for use in an SRAM array. The memory cell 100 includes a static storage element 102 which is connectable to first and second write bit lines (WBL) 104 and 106 via first and second write access circuits 128 and 130, respectively. Write access circuits 128 and 130 include access transistors 114 and 116, respectively, although alternative connection circuitry can also be used.
Gate terminals of access transistors 114 and 116 are connected to a corresponding write word line (WWL) 110 for conveying a write signal. The access transistors 114 and 116 function together to connect the storage element 102 to the write bit lines (WBL) 104 and 106 in response to a write signal. The first and second write access circuits 128 and 130 may be implemented as a single write circuit.
As technologies scale, process-induced variations, as well as fundamental variation sources such as the dopant fluctuation effect on Vt (voltage threshold) result in large threshold voltage variations across a wafer.
This Vt scatter magnifies the disturb voltage in 6-T cells, which leads to stability fails in SRAM arrays. The scaling of power supply voltages further degrades stability. Existing solutions involve subtle modifications to the 6-T cell itself such as transistor sizing, threshold voltage design, increasing cell size; or the array, such as a higher static random access memory (SRAM) array power supply voltage (Vdd) to increase the stability margin. These techniques may not be sufficient in future technologies.
Therefore, there is a need for a method to improve SRAM stability as CMOS technologies are scaled.